This application claims the priority benefit of Taiwan application serial no. 88104901, filed Mar. 29, 1999.
1. Field of the Invention
The invention relates to a chip set for controlling a graphic system, and more particularly, to a chip set comprising only one graphic interface reference voltage pin for controlling a accelerating graphic system of an accelerated graphics port (AGP).
2. Description of the Related Art
Though being widely applied, the three-dimensional graphic system has a very low operation speed due to large quantity of data to be processed. To resolve the problem of an input/output jam, a new channel has been developed by manufactures. The new channel, that is, an accelerated graphics port is used to directly connect a graphic chip and a chip set on a mother board. Currently, the accelerated graphics port includes a single-edge-clocked (1xc3x97), a double-edge-clocked (2xc3x97), and a quad-edge-clocked (4xc3x97) transfer modes to transfer data between the graphic chip and the chip set for controlling the accelerating graphic system.
FIG. 1 schematically shows a reference voltage circuit of the accelerated graphics system while an accelerated graphics port is operated under a single-edge-clocked transfer or a double-edge-clocked transfer mode. The reference input/output supply voltage Vddq of the mother board is 3.3 volt. The chip set 10 is coupled to the mother board with a divided voltage of the reference input/output supply voltage VDDQ of about 1.32 volt as a reference voltage.
In FIG. 2, shows a schematic drawing of a reference voltage circuit of the accelerated graphics system while an accelerated graphics port is operated under a quad-edge-clocked transfer mode. Since the operation speed of the quad-edge-clocked transfer mode is faster, an internal reference voltage required by the chip set is smaller to obtain the faster operation. Under the quad-edge-clocked transfer mode, the internal reference voltage of the accelerated graphics system is often of about 0.75 volt. However, with a smaller internal reference voltage, the chip set very often fails to determine a correct answer according to an input detecting potential while the reference input/output supply voltage of the mother board is unstable. To solve this problem, the internal reference voltage of the core circuit 21 in the chip set 20 uses a reference input/output supply voltage of a display card provided by the mother board as a voltage source. After being divided, the source voltage is provided to the core circuit 21 via a pin 25 of an accelerated graphics port 24. Similarly, a graphic chip 23 on the display card 22 uses a divided voltage of the reference input/output supply voltage provided by the mother as a voltage source via another pin of the accelerated graphics port 24. The divided voltages of both the graphic chip 23 and the core circuit 21 are the same. Therefore, under a circumstance that the reference input/output supply voltage is unstable, though the reference voltages of the graphic chip 23 and the core circuit 21 jump accordingly, the potential difference between these two divided voltages remain constant. The data determination is thus unaffected.
In FIG. 3, a reference voltage circuit of a accelerated graphics system applicable for operations under a single-edge-clocked, a double-edge-clocked, and a quad-edge-clocked transfer modes is shown. According to specific requirement, many chip sets are designed to work under different transfer modes. A chip set 30 comprises two pins coupled to an internal reference voltage source. One of the pins is coupled to a mother board 36 to receive the internal reference voltage from the mother board while the accelerated graphics port 34 is operated under the single-edge-clocked or the double-edge-clocked transfer mode. Whereas, the other pin is coupled to an accelerated graphics port 34 to obtain the internal reference voltage while the accelerated graphics port 34 is operated under the quad-edge-clocked transfer mode. However, apart from the very complex connection, additional pins are required for the chip sets. Typically, the internal layout of the chip set is complex enough. With an additional internal reference voltage source, the layout problem becomes even more complex.
The invention provides a chip set comprising only one graphic interface reference voltage pin. The chip set comprises a comparator, a multiplexer (MUX), and a core circuit. The comparator is used to compare to a reference input/output supply voltage with a mode determining reference voltage and to generate a mode signal according to the comparing result. The multiplexer is coupled to the comparator and an accelerated graphics port, so that an internal reference voltage is output thereby according to the mode signal generated by the comparator. The internal reference voltage can be either a division of the Reference input/output supply voltage or a graphic interface reference voltage provided by a display card. The core circuit is connected to the multiplexer. Using the internal reference voltage output by the multiplexer as reference, the input detecting potential level of the interface signal of the accelerated graphics port is determined.
The invention further provides a mother board system. The mother board and the accelerated graphics port are coupled to multiplexer, wherein the accelerated graphics port has two pins connected to the multiplexer. One of these two pins provides a graphic interface reference voltage, while the other provides a mode signal. The multiplexer thus selects an output of an internal reference voltage from either the Reference input/output supply voltage or the graphic interface reference voltage according to the mode signal.
In the invention, the chip set comprising only one graphic interface reference voltage pin to receive a graphic interface reference voltage thereby. The layout complexity of the chip sets applicable for accelerated graphics ports operated under different transfer modes is greatly reduced. Moreover, the reduction of the number of pins reduces the fabrication cost.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.